1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to semiconductor devices having double lightly doped regions for improved DRAM refresh characteristics and methods for their manufacture.
2. Description of the Related Art
Metal oxide semiconductor (MOS) structures are basic electronic devices used in many integrated circuits. One such structure is the MOS field effect transistor (MOSFET), which is typically formed in a semiconductor substrate by providing a gate structure over the substrate to define a channel region, and by forming source and drain regions on opposing sides of the channel region.
MOSFETs are often used in the formation of memory circuits, including dynamic random access memory (DRAM) circuits. DRAM circuits are composed of an array of individual memory cells, each cell including a capacitor for holding a charge and an access transistor for accessing the charge held in the capacitor.
In a typical DRAM cell using a MOSFET access transistor, after a charge is stored the charge does not remain in the capacitor indefinitely, but instead slowly leaks out of the p-n junction of the access transistor for the cell. This phenomenon is known as xe2x80x9cjunction leakage.xe2x80x9d To avoid losing the cell contents, the charge must be periodically re-stored in the capacitor through a process known as xe2x80x9crefresh.xe2x80x9d Increased junction leakage leads to premature depletion of the capacitor""s stored charge, necessitating more frequent refresh operations. Refresh operations consume device resources and it is therefore desirable to reduce junction leakage as much as possible and thus reduce the frequency of required refresh operations.
Several factors are known to contribute to junction leakage, including (a) the electric field (E) generated at the p-n junction, (b) surface- or bulk-defect-induced recombination/generation current, and (c) gated diode assisted band-to-band tunneling leakage, such as gate-induced drain-leakage (GIDL) current. In particular, factor (a), the electric field (E) generated at the p-n junction, is proportional to the gradient of the doping concentration of either side of the junction. Because junction leakage varies directly with this electric field (i.e. higher E leads to higher junction leakage), it is desirable to control the doping concentration on both sides of the p-n junction. By controlling the doping concentration on both sides of the junction to reduce the gradient of the doping concentration, the p-n junction electric field (E) can be reduced and hence junction leakage.
The gradient of the doping concentration at the p-n junction of a MOSFET in a DRAM array depends on the doping concentration of the channel region and the doping concentration of the ion-implanted regions adjacent the channel serving as source/drain regions for a cell access transistor. For example, in an NMOS transistor, the channel is doped with p-type impurities, the source and drain regions are doped with n-type impurities, and as the boundary between the p-type channel and the n-type drain region is approached, the rate of change in impurity concentration defines the gradient of the doping concentration. An abrupt change in impurity concentration from p-type to n-type doping at the boundary creates a high gradient, high electric field (E) and hence increases junction leakage. A more gradual change from p-type to n-type doping concentration, for example using lightly doped drain (LDD) regions, creates a relatively lower gradient, lower electric field (E) and hence decreases junction leakage.
There are several tradeoffs that must be taken into account when formulating the doping concentrations on either side of the p-n junction. For example, in an NMOS transistor, the p-type doping concentration of the channel should be sufficiently high to turn off the transistor when the gate is off (i.e., low subthreshold leakage). On the other hand, the channel doping concentration should not be so high that a full potential of charge is prevented from being transferred from source to drain when the gate is on.
Likewise, the n-type doping concentration of the source and drain regions should be sufficiently high to obtain satisfactorily low series resistance and threshold voltage. If the n-type doping concentration is too low, transistor current drive may be degraded and a wider depletion width may result, possibly leading to undesirable levels of reverse bias current. On the other hand, if the n-type doping concentration is too high, undesirable junction leakage effects can result as discussed above. Thus, it would be desirable to form the memory array taking the above considerations into account and produce memory cells in which the electric field generated at the p-n junction is reduced for each cell and hence reduce junction leakage.
Another problem associated with the electric field generated at the p-n junction is the xe2x80x9chot carrierxe2x80x9d or xe2x80x9chot electronxe2x80x9d effect wherein energetic charge carriers, typically electrons and/or holes, are accelerated by a strong electric field, such as that created at the p-n junction. Such high strength electric fields accelerate the energetic carriers, known as xe2x80x9chot carriers,xe2x80x9d toward the gate electrode and the underlying gate oxide. These hot carriers are thus injected into the thin dielectric layer of the gate structure and into the adjacent thicker dielectric gate spacer structure, resulting in damage to the gate oxide as well as to the gate spacer structure. Over time, these hot electrons create a permanent charge in the thin dielectric layer and the dielectric spacers, degrading or destroying the performance of the associated MOSFET device. This is typically more of a problem with N-channel MOSFETS (which have electrons as the primary carrier species) than P-channel MOSFETS (which have xe2x80x9cholesxe2x80x9d as the primary carrier species).
The above problems are well known in the art and have resulted in the widely practiced remedy of forming lightly doped drain (LDD) regions between the source/drain regions and the channel region in the semiconductor substrate. This LDD region reduces the gradient of the doping concentration at the boundary (p-n junction) between the source/drain regions and the channel region to thereby lower the strength of the electric field (E) generated at the p-n junction. This reduction in the electric field (E) results in decreased junction leakage and reduces the hot carrier effect.
For example, U.S. Pat. No. 4,366,613 to Ogura et al. (xe2x80x9cOguraxe2x80x9d) discloses the formation of LDD regions in a RAM MOSFET. Referring to FIG. 1, MOSFET device 5 includes a gate structure comprising an access gate conductor 16 and a gate top insulator 20 formed over an oxide layer 18 that is formed on a substrate 12. Insulating spacers 32, 34 are formed on sidewalls of the gate structure. The device also includes source/drain regions 36, 38 and two lightly doped regions 22 and 24, one of which is provided proximate to each of the source/drain regions 36, 38. A channel 15 extends between the LDD regions 22 and 24. By providing the LDD regions 22 and 24, the electric field at the p-n junction between the channel 15 and the source/drain regions 36, 38 is reduced, thereby reducing the junction leakage and the hot carrier effect.
The prior art LDD structure of FIG. 1 can be made by a variety of processes, but is typically made by providing a low-density ion implant of the LDD regions 22, 24 before adding oxide spacers 32, 34 to the gate structure (see U.S. Pat. No. 4,366,613 to Ogura). After the spacers 32, 34 have been added to the gate structure, a higher-density ion implant is made to form the source and drain regions 36, 38. Since the source and drain regions 36, 38 were implanted after the formation of the spacers 32, 34, they are offset further from the channel 15 than the LDD regions 22, 24. The resulting structure exhibits a decreased electric field at the p-n junction.
Although LDD structures have helped advance the state of the art, increasing competition in the semiconductor industry, particularly in the development of DRAM devices and methods, have created a need and desire for greater device performance, especially in the area of lower refresh rates. It would, therefore, be desirable if the problems of junction leakage and hot carrier generation at the p-n junction could be further reduced in a MOSFET access transistor of a memory cell, using conventional processing and manufacturing techniques and at a reasonable cost.
The present invention provides a technique for forming double LDD regions at the p-n junction of a MOSFET access transistor of a memory cell that reliably improves the refresh characteristics of DRAM memory devices without substantially increasing manufacturing costs, with the added benefit of LDD peripheral devices resistant to hot carrier effects.
The above and other features and advantages of the invention are achieved by providing a DRAM memory circuit composed of novel integrated circuit devices, and a novel method of making the devices, including a memory cell with an access transistor with double LDD regions in addition to lightly doped LDD regions in a conventional metal oxide semiconductor field effect transistor (MOSFET), with or without using an additional mask. In the process of making the devices, a semiconductor substrate is provided with a gate structure formed on its surface, thereby defining a channel region in the substrate beneath the gate having a source side and a drain side. Next, lightly doped LDD regions are formed adjacent to the channel region by ion implantation in the substrate. Then, insulating spacers of a first width are formed adjacent to the sidewalls of the gate structure covering at least a portion of each of the LDD regions. Next, the memory array portion of the DRAM circuit is masked and heavily-doped source/drain regions are formed in the unmasked periphery MOSFETs by ion implantation in the substrate. The mask is then removed, and the insulating spacers are etched back to a second width smaller than the first width. Then, double LDD regions are formed by lightly doping the substrate in the memory array and in the periphery MOSFET areas. The structures formed in this method permit reduced channel doping in the memory array, reduced doping concentration gradient near the p-n junction, and hence a reduced electric field at the p-n junctions in both the memory array and peripheral MOSFETS.
The present invention thus provides an improved doping profile at the p-n junction between the channel and the source/drain regions, thereby improving DRAM refresh characteristics by reducing junction leakage. In addition, the hot carrier effect is reduced for periphery MOSFETs. Furthermore, these favorable results were obtained using conventional masking and etching techniques, obviating the need for unconventional processing techniques at a higher cost and failure rate.